Corvus
Investigationd1b203e4

Market analysis

Analysis

Positioning

Concentrated merchant-incumbent market: NVIDIA dominates with 80-92% data-center AI accelerator revenue share; AMD is the principal merchant challenger; hyperscaler custom ASICs co-designed with Broadcom are the structurally most credible long-term threat; TSMC CoWoS and HBM supply are the binding physical constraints; US export controls have bifurcated the market with Huawei Ascend as the PRC-domestic substitute.

Competitors

SWOT

Strengths
  • Demand-side tailwind: hyperscaler capex commitments at $600-725B for 2026 (Big Four), ~75% directed at AI infrastructure Anchors a multi-year, multi-hundred-billion-dollar order book for the whole accelerator + packaging + memory + networking stack
  • Mature software moat (CUDA) at the incumbent that compounds as the installed base grows CUDA + cuDNN + NCCL + TensorRT-LLM is the highest single switching cost in the industry; ROCm, XLA, Triton are closing the gap only slowly
  • Diversified credible alternatives across multiple architectural approaches Merchant GPUs (AMD), wafer-scale (Cerebras), inference-only ASIC (Groq), reconfigurable (SambaNova), hyperscaler ASIC (TPU/Trainium/Maia/MTIA), and PRC-domestic NPU (Huawei) — collectively reduce single-vendor concentration risk to buyers
Weaknesses
  • Single-vendor revenue concentration at NVIDIA (~80-92% data-center share) Industry-level price discovery, software stack evolution, and supply allocation are all set by one firm — and that firm's decisions about which customers, geographies, and SKUs to prioritise become market structure
  • Severe physical bottleneck at TSMC CoWoS + HBM Estimated ~90% of global advanced packaging and HBM consumed by the top four AI designers in 2025; ramp from 65-75K WPM (2025) to 90-110K WPM (2026) still trails demand
  • Geographic concentration risk at TSMC / Taiwan Sole-source dependence on a single island for advanced AI accelerator production is the dominant supply-chain risk
  • Software-fragmentation risk on the non-NVIDIA path ROCm, XLA, MLIR, vendor-specific compilers for TPU/Trainium/Maia/MTIA/Huawei increase porting cost; every additional accelerator increases developer-tooling debt
Opportunities
  • Inference workload share rises faster than training, expanding the market faster than NVIDIA can serve it Test-time compute / agentic workloads (long-context, multi-step) push inference compute consumption per token higher; favors lower-cost ASICs and inference-specialist clouds
  • Custom-ASIC programs at every major hyperscaler create a $30B+ ASIC sub-market growing >30% per year Broadcom and Marvell are direct beneficiaries; the structural shift dwarfs the merchant-challenger story in size
  • PRC-domestic stack (Huawei Ascend + SMIC) opens a $10B+ parallel market under US export controls Permanent bifurcation gives Huawei a captive demand pool inside China at scale; 2025 production at ~400k Ascend 910C units
  • Inference-cloud business model (Cerebras, Groq, neoclouds) lets challengers sell capacity rather than chips Decouples the customer adoption decision from CUDA software lock-in and removes the upfront capex barrier
Threats
  • Hyperscaler capex sustainability if monetisable AI revenue lags $600-725B aggregate Big Four capex 2026 requires a commensurate increase in AI-monetised revenue downstream; if it slips, the merchant accelerator pricing structure compresses sharply
  • US BIS export-control regime can swing in either direction with little notice Apr 2025 H20 freeze removed ~$16B / 1.3M-unit pipeline overnight; Jan 2026 brought a partial relaxation — the policy uncertainty is itself a structural cost
  • Customer-base concentration risk at challengers (single-customer revenue) Cerebras revenue 85% G42 in 2024, 62% MBZUAI in 2025 — typical of the inference-specialist cohort and a clear IPO-risk-factor
  • Taiwan geopolitical risk Any disruption to TSMC's Hsinchu / Tainan / Kaohsiung fabs would cause a worldwide AI chip shortage of unprecedented scale

Porter's Five Forces

Threat of New Entry low

Greenfield entry requires: a credible chip-design team (years), TSMC CoWoS allocation (allocation rights, not just dollars), HBM supply (allocation), $100M+ of mask + design costs per generation, and a software stack to compete with CUDA. The 2025-2026 wave of new entrants are essentially the existing hyperscalers using Broadcom/Marvell to bridge the design gap; no plausible standalone new entrant has emerged outside that pattern.

Supplier Power high

TSMC controls ~70% of foundry share and is sole-source for advanced AI accelerator packaging via CoWoS; HBM is a three-supplier oligopoly (SK hynix, Samsung, Micron). The dominant suppliers can — and do — allocate capacity by customer priority, and ramp constraints persist through 2027.

Competitive Rivalry moderate

One vendor (NVIDIA) holds 80-92% revenue share, which structurally suppresses head-to-head price rivalry; the real rivalry happens architecturally between NVIDIA GPUs and hyperscaler custom ASICs at the buy-vs-build decision, plus within the merchant inference-specialist cohort fighting over a smaller pool.

Buyer Power moderate

Buyer base is highly concentrated (Big Four hyperscalers + a small group of frontier labs and sovereign AI buyers), which in principle confers buyer power. But supply scarcity inverts the relationship — buyers compete for allocation rather than negotiate price down. The largest buyers exercise their power through ASIC programs (build-instead-of-buy) rather than price negotiation.

Threat of Substitution moderate

Substitutes exist (hyperscaler ASICs, merchant challengers, PRC-domestic stack) and are gaining share at the margin, but the CUDA software moat plus inertia in production ML pipelines limits the speed of substitution. Inference workloads substitute more readily than training; PRC market is fully substituted by export-control mandate.